SyNAPSE: Synthesizing Network Accelerators using Programmable Switching Equipment
When implementing network functions (NFs), developers are often confronted with a choice: implement the NF in software and face the challenge of performance, or use one of a wide variety of programmable networking devices, such as programmable switches and SmartNICs, to trade-off some flexibility for the ability to process packets at full line rate.
With SyNAPSE we ask "Why not have both?". We propose a synthesis based approach to automatically generate accelerated implementations of a Software NFs, using smart network devices whenever possible to increase performance.
Further Reading
Main Website: https://synapse.inesc-id.pt/
Francisco Pereira, Gonçalo Matos, Hugo Sadok, Daehyeok Kim, Ruben Martins, Justine Sherry, Fernando M. V. Ramos, and Luis Pedrosa; Automatic Generation of Network Function Accelerators Using Component-Based Synthesis. In 2022 Symposium on SDN Research (SOSR'22). 2022
People
- Francisco Pereira (IST - U. Lisbon)
- Gonçalo Matos (IST - U. Lisbon)
- Hugo Sadok (CMU)
- Daehyeok Kim (Microsoft Research)
- Francisco Machado (IST - U. Lisbon)
- João Tiago (IST - U. Lisbon)
- Justine Sherry (CMU)
- Ruben Martins (CMU)
- Fernando Ramos (IST - U. Lisbon / INESC-ID)
- Luis Pedrosa (IST - U. Lisbon / INESC-ID)